1. Field of the Invention
The invention relates generally to a transistor in a semiconductor device and method of manufacturing the same, and more particularly to, a transistor in a semiconductor device and method of manufacturing the same, capable of improving a refresh operating characteristic of a DRAM device and preventing generation of a coupling noise.
2. Description of the Prior Art
Generally, as the integration level of a semiconductor device becomes higher, the width of a gate electrode and a channel in a transistor becomes narrow and the depth of a source and a drain becomes shallows. Even though, there is a need for a transistor of a high performance. Further, as the semiconductor device becomes highly integrated, it is difficult to individually define respective contact patterns since the size of a contact and the distance between the contacts are very small in patterning a bit line contact and a storage node contact in a cell. In order to solve this problem, a method is usually employed by which the bit line contact and the storage node contact are separated from the hard mask layer formed on the gate electrode by a chemical mechanical polishing method using an etch barrier, after a large contact pattern is formed by a self-aligned contact etch process at a time.
FIGS. 1Axcx9c1C are cross-sectional views of a conventional semiconductor device for describing a method of manufacturing a transistor in the device;
Referring now to FIG. 1A, a device isolation film 12 is formed in a semiconductor substrate 11 to define an active region. Then, a gate oxide film 13, a gate electrode 14 and a hard mask layer 15 are sequentially stacked on the semiconductor substrate 11 in which the device isolation film 12 is formed. An oxide film 16 is formed at the sidewall of the gate electrode 14 and the exposed surface of the semiconductor substrate 11 by means of gate re-oxidation process.
In the above, the device isolation film 12 is formed using a shallow trench isolation (STI) process for higher-integration of the device. The hard mask layer 15 is formed of a nitride-series material.
Referring now to FIG. 1B, a source 17s and a drain 17d are formed in the semiconductor substrate 11 by a source/the drain ion implantation process. An insulating film spacer 18 is formed at the sidewall of a stack structure including the gate electrode 14 and the hard mask layer 15.
In the above, the insulating film spacer 18 is formed of a nitride-series material same to the hard mask layer 15.
Referring now to FIG. 1C, an inter-dielectric layer 19 is formed on the entire structure including the insulating film spacer 18. Contact holes through which the source 17s and the drain 17d are exposed, respectively, are formed by a self-aligned contact mask process and an etch process of the interlayer insulating layer 19. Next, a storage node contact 20 connected to the source 17s and a bit line contact 21 connected to the drain 17d are formed.
In the above, polysilicon is deposited and an etch-back process or a chemical mechanical polishing (CMP) process is performed to form the storage node contact 20 and the bit line contact 21.
General processes such as processes of forming bit lines, capacitors and metal wires are performed to complete a semiconductor device.
A space of each of the storage node contact and the bit line contact with the gate electrode is narrowed due to higher integration of the semiconductor device. Due to this, a problem such as an electrical short is caused. Also, as a zero (0) voltage is applied to the gate electrode in a refresh operation mode of a DRAM device and high date is stored at the storage node, there is a problem that a gate induced drain leakage (GIDL) current is generated by the difference in the voltage between the gate electrode and the storage node to degrade the refresh operating characteristic of the DRAM device. Further, as the gate electrode is continuously turned on/off, there is a problem that a normal operation of the DRAM is adversely affected by a coupling phenomenon due to a parasitic capacitance between the bit line and the gate electrode.
It is therefore an object of the present invention to provide a transistor in a semiconductor device and method of manufacturing the same, capable of improving a refresh operating characteristic of a DRAM device and preventing generation of a coupling noise.
In order to accomplish the above object, a transistor in a semiconductor device according to the present invention, is characterized in that it comprises a gate electrode electrically isolated from the semiconductor substrate by a gate oxide film and connected to a first power supply source; a source formed in the semiconductor substrate at one side of the gate electrode; a drain formed in the semiconductor substrate at the other side of the gate electrode and formed oppositely to the source; and an auxiliary electrode formed at both sides of the gate electrode, electrically isolated from the gate electrode, the source and the drain, respectively, by means of the oxide film and connected to a second power supply source.
In the above, upon an on operation of the transistor, the same voltage to a voltage applied to the gate electrode is applied to the auxiliary electrode.
Also, a method of manufacturing a transistor in a semiconductor device according to the present invention, is characterized in that it comprises the steps of forming a structure in which a gate oxide film, a gate electrode and a hard mask layer are stacked on a semiconductor substrate in which a device isolation film is formed; forming an oxide film at the sidewall of the gate electrode and an exposed surface of the semiconductor substrate; forming a source and a drain in the semiconductor substrate; forming an auxiliary electrode at the sidewall of the stack structure including the gate electrode and the hard mask layer; forming an insulating film spacer connected to the hard mask layer on the auxiliary electrode; forming a storage node contact connected to the source and a bit line contact connected to the drain; and connecting a first power supply source to the gate electrode and a second power supply source to the auxiliary electrode, in a subsequent process of forming a metal wire.
In the above, the auxiliary electrode is formed by depositing a conductive material such as polysilicon, tungsten, aluminum, tungsten silicide, tungsten nitride or the like and then performing a reactive ion etching process. Upon the reactive ion etching process, over-etch is performed to position an upper side of the auxiliary below an upper side of the stack structure.